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Product Proposal
HCS12DBFAMILYPP/D Rev. 0.7, 8/2003 HCS12DB Family Product Proposal
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Introduction
Designed for automotive multiplexing applications, members of the MC9S12DB-Family of 16 bit Flash-based microcontrollers are fully pin compatible and enable users to choose between different memory and peripheral options for scalable designs. All MC9S12DB-Family members are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), up to two serial peripheral interfaces (SPI), an enhanced capture timer (ECT), two 8channel, 10-bit analog-to-digital converters (ADC), an eight-channel pulsewidth modulator (PWM), Byteflight interface and up to two CAN 2.0 A, B software compatible modules (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM). The MC9S12DB-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with Wake-Up capability from STOP or WAIT mode.
Table 1. MC9S12DB Family Members
Flash 128K 64K RAM 8K 8K EEPROM 2K 2K Package 112 LQFP 80 QFP 80 QFP Device MC9S12DB128 MC9S12DB64 CAN 2 0 0 Byte Flight 1 1 1 SCI 2 1 1 SPI 2 2 1 A/D 2/16 1/8 1/8 PWM 8 ch 7 ch 7 ch I/O 91 59 59
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HCS12DBFAMILYPP/D
Features NOTE:
Not all features listed here are available in all configurations. * 16-bit CPU12 - Upward compatible with M68HC11 instruction set - Interrupt stacking and programmer's model identical to M68HC11 - 20-bit ALU - Instruction queue - Enhanced indexed addressing Multiplexed bus - Single chip or expanded - 16 address/16 data wide or 16 address/8 data narrow modes - External address space 1 MB for data and program space (112 pin package only) Wake-up interrupt inputs depending on the package option - 8-bit port H - 4-bit port J - 8-bit port shared with PWM/SPI Memory options - 64K, 128K Byte Flash EEPROM - 2K Byte EEPROM - 8K Byte RAM One or Two analog-to-digital converters (ATD) - 1 or 2 times 8-channels, 10-bit resolution depending on the package option - External conversion trigger capability Up to two 1 M bit per second, CAN 2.0 A, B software compatible modules - Five receive and three transmit buffers - Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit - Four separate interrupt channels for Rx, Tx, error and wake-up - Low-pass filter wake-up function - Loop-back for self test operation Enhanced Capture Timer (ECT) - 16-bit main counter with 7-bit prescaler - 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer - Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four - Four 8-bit or two 16-bit pulse accumulators - 16-bit modulus down-counter with 4-bit prescaler - Four user-selectable delay counters for signal filtering
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HCS12DB Family Product Proposal
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HCS12DBFAMILYPP/D Features
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Seven or eight PWM channels with programmable period and duty cycle - 8-bit 4-channel or 16-bit 2-channel (80-Pin Version) - 8-bit 8-channel or 16-bit 4-channel (112-Pin Version) - Separate control for each pulse width and duty cycle - Center- or left-aligned outputs - Programmable clock select logic with a wide range of frequencies Serial interfaces - Two asynchronous serial communications interfaces (SCI) - Up to two synchronous serial peripheral interfaces (SPI) Byteflight - 10 MBit/s serial protocol SIM (system integration module) - CRG (windowed COP watchdog, real-time interrupt, clock monitor, clock generation and reset) - MEBI (multiplexed external bus interface) - MMC (memory map and interface) - INT (interrupt control) - BKP (breakpoints) - BDM (background debug mode) Clock generation - Phase-locked loop clock frequency multiplier - Limp home mode in absence of external clock - Slow mode divider - Low power 0.5 to 40 MHz crystal oscillator reference clock Operating frequency - 50 MHz equivalent to 25 MHz bus speed for single chip - 40 MHz equivalent to 20 MHz bus speed in expanded bus modes Internal 5 V to 2.5 V regulator 112-Pin LQFP or 80-Pin QFP package - I/O lines with 5-V input and drive capability - 5-V ATD inputs - Dual supply (5 V for I/O and ATD, 2.5 V for logic Development support - Single-wire background debugTM mode (BDM) - On-chip hardware breakpoints
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HCS12DBFAMILYPP/D
64K or 128K Byte Flash EEPROM 8K Byte RAM 2K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST
ATD0
VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07
ATD1
VRH VRL VDDA VSSA
VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19
Voltage Regulator
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD MISO MOSI SCK SS
AD0
Single-wire Background Debug Module
Clock and Reset Generation Module
CPU12
DDRK
PPAGE
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PLL
Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PTK
AD1
ECS
XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS
DDRE
PTE
Enhanced Capture Timer
DDRT DDRS
SCI0
PTS
Multiplexed Address/Data Bus SPI0 DDRA PTA
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
CAN0
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
BYTEFLIGHT
RxCAN TxCAN RX_BF TX_BF BF_PSYN BF_PROK BF_PERR BF_PSLM KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
DDRJ
CAN4
Multiplexed Narrow Bus
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
RxCAN TxCAN PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS
DDRP
VDD1,2 VSS1,2
VDDX VSSX
PLL 2.5V
VDDPLL
A/D Converter 5V & Voltage Regulator Reference
VDDA VSSA
PWM
VSSPLL
PTP
Internal Logic 2.5V
I/O Driver 5V
PTJ
Multiplexed Wide Bus
PTH
SPI1 Voltage Regulator 5V & I/O
VDDR VSSR
DDRH
PH2
PH3 PH4 PH5 PH6 PH7
Not all functionality shown in this block diagram is available in all versions.
Figure 1. MC9S12DB Family Block Diagram
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HCS12DB Family Product Proposal
Signals shown in Bold are not available on the 80 QFP Package
SCI1
DDRM
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
PTM
PTT
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HCS12DBFAMILYPP/D Pin Out Explanations:
Pin Out Explanations:
* * A/D is the number of modules/total number of A/D channels. I/O count: - 112 Pin Package: - Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, - PAD = 16 input only. - 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) - 80 Pin Package: - Port A = 8, B = 8, E = 6 + 2 input only, M = 6, P = 7, S = 6, T = 8, PAD = 8 input only - 9 inputs provide Interrupt capability (P= 7, IRQ, XIRQ) MC9S12DB64 features only one SPI, SPI0 SPI1 pins are shared with PWM3:0 or Port H3:0 routeable under software control
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* *
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HCS12DBFAMILYPP/D
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Figure 2. Pin Assignments 112 LQFP for MC9S12DB128
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4 PP5/KPW5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS/ROMCTL VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RX_BF/RXCAN0/MISO0 PM3/TX_BF/TXCAN0/SS0 PM4/BF_PSYN/RXCAN0/RXCAN4/MOSI0 PM5/BF_PROK/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA PJ7/KWJ7/TXCAN4/SCL VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/BF_PERR/RXCAN4 PM7/BF_PSLM/TXCAN4 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
MC9S12DB128
112LQFP
VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Signals shown in Bold are not available on the 80 Pin Package
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HCS12DBFAMILYPP/D Pin Out Explanations:
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM2/RX_BF PM3/TX_BF PM4/BF_PSYN PM5/BF_PROK VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS1/TXD0 PS0/RXD0 PM6/BF_PERR BF_PSLM VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
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MC9S12DB128
80 QFP
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 3. Pin Assignments MC9S12DB128 in 80 QFP
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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HCS12DBFAMILYPP/D
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM2/RX_BF PM3/TX_BF PM4/BF_PSYN PM5/BF_PROK VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS1/TXD0 PS0/RXD0 PM6/BF_PERR BF_PSLM VSSA VRL PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
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MC9S12DB64
80 QFP
VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8
Figure 4. Pin Assignments MC9S12DB64 in 80 QFP
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ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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HCS12DBFAMILYPP/D Pin Out Explanations:
$0000 $0000 $0400 $0800 $1000 $2000 $03FF $0800 $0FFF $2000 $3FFF $4000 $4000
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary 0.5K, 1K, 2K or 4K Protected Sector
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$7FFF $8000 $8000 EXT $BFFF $C000 $C000
16K Fixed Flash EEPROM
16K Page Window Eight * 16K Flash EEPROM Pages
16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The address does not show the map after reset, but a useful map. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM $0000 - $07FF: 2K EEPROM (not visible)
Figure 5. MC9S12DB128 User Configurable Memory Map
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$0000 $0000 $0400 $0800 $0C00 $1000 $3000 $4000 $03FF $0800
1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM
$0FFF $2000 $3FFF
Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 4K Boundary
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$4000
0.5K, 1K, 2K or 4K Protected Sector
$8000
$7FFF $8000 EXT
16K Fixed Flash EEPROM 16K Page Window four * 16K Flash EEPROM Pages
$BFFF $C000 $C000 16K Fixed Flash EEPROM
$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM $0000 - $07FF: 2K EEPROM (not visible)
Figure 6. MC9S12DB64 User Configurable Memory Map
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HCS12DBFAMILYPP/D Pin Out Explanations:
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HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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HCS12DBFAMILYPP/D

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